(a) Field of the Invention
The present invention relates to a signal receiver for receiving data in an interface of a micro-processing unit (MPU), a memory and so forth from an input/output line.
(b) Description of the Related Art
With the increase of operating frequency in an MPU up to 50 MHz, a limit has appeared, from the viewpoint of electric power consumption or switching noise, in a conventional interface which connects the MPU, a memory and so forth with an input/output line and has been used for a long time. In such a situation, i is important to develop a new interface operating in a high-speed. Some interfaces capable of operating in a high-speed are proposed recently. One of those is especially expected to be an interface operating in a high speed. FIGS. 1A, 1B and 1C show the proposed interface, a driver and a signal receiver in the interface, respectively.
In FIG. 1A, the signal transmission circuit connecting an MPU 501 to a plurality of memories 502 is comprised of interfaces each including a pair of driver 503 and signal receiver 504 and provided in the MPU 501 and the respective memories 502, a referential voltage power supply line 506, an input/output line 508 and terminating resistors R1.
The MPU 501 and each of the memories 502 transmit data between them by using the drivers 503, signal receivers 504 and input/output line 508. For example, the data is transmitted from the driver 503 in the MPU 501 to the input/output line 508, from which the data is read by the signal receiver 504 in tile memory 502 provided specifically for receiving data from the input/output line 508.
The terminating resistors R1 are connected between the input/output line 508 and the referential voltage supply line 506 at both ends of the input/output line 508, in order to avoid noise generated by signal reflection at the terminals of the input/output line 508.
Now, examples of actual circuits of the conventional driver 503 and signal receiver 504 will be described with reference to FIG. 1B and FIG. 1C, respectively.
In FIG. 1B, the driver 503, referred to as a three-state buffer, is comprised of two field effect transistors Q41 and Q42. The source of the p-channel (p-ch) transistor Q41 is connected to a power supply line V.sub.cc, while the source of n-ch transistor Q42 is connected to the ground GND. Each of the gates of transistors Q41 and Q42 is connected to a signal line receiving an input signal V.sub.DIN. Both the drains of transistors Q41 and Q42 are connected together to the input/output line 508.
In the configurations as described above, when a low-level signal V.sub.DIN is input to turn transistor Q41 on and transistor Q42 off, an output voltage having nearly the same potential as that of the supply line V.sub.cc is output to the input/output line 508. On the other hand, when a high-level signal is input to turn transistor Q42 on and transistor Q41 off, an output voltage having nearly the same potential as the ground potential GND is output to the input/output line 508. Further, if a high- or low-level signal is not supplied to the driver input line, both transistors Q41 and Q42 are turned off, so that the output of the driver 503 is kept at a high impedance state. Data are thus transmitted from the driver 503 to the input/output line 508.
In FIG. 1C, the signal receiver 504 is comprised of a differential amplifier 522 and an inverter 521 receiving the output of the differential amplifier 522. The differential amplifier 522 includes p-oh transistors Q53 and Q58 each having a gate receiving an activation signal. PSW by which the differential amplifier 522 is turned active or inactive, and p-ch transistors Q54, Q59 and n-ch transistors Q55, Q60 constituting the body of the differential amplifier 522. Each of the sources of transistors Q53 and Q58 is connected to the power supply line V.sub.cc, and the drains off transistor Q53 and Q58 are connected to the sources of transistors Q54 and Q59, respectively. When the receiver 504 is to be activated, transistors Q53 and Q58 are turned on by lowering the activation signal PSW at a low level to supply the electric power to transistors Q54, Q55, Q59 and Q60 constituting the body of the differential amplifier 522. 0n the other hand; when the signal receiver 504 is not to be activated, the signal receiver 504 is kept at a high impedance state by raising the activation signal PSW at a high level.
Each of the sources of transistors Q55 and Q60 of the differential amplifier 522 is connected to the ground GND. The gate of transistor Q55 is connected to the input/output line 508, and an input signal V.sub.in for the receiver 504 is supplied thereto. The referential voltage supply line 506 is connected to the gate of transistor Q60, and the referential voltage V.sub.ref is supplied thereto. The drains of transistors Q59 and Q60 and the gates of transistors Q54 and Q59 are connected together, respectively. Each of the drains of transistors Q54 and Q55 are connected together to an output 520 of the differential amplifier 522. The output 520 of the differential amplifier 522 is connected to an input to the inverter 521, the output of which is connected to the internal circuit (not shown) of corresponding one of memories and MPU in the system.
In operation, the differential amplifier 522 detects, with a high sensitivity, very small potential difference between the potential of the input signal V.sub.in from the input/output line 508 and the referential voltage V.sub.ref, amplifies the small potential difference and outputs an output signal V.sub.so through the output 520 of the differential amplifier 522. When the input signal V.sub.in is higher than the referential voltage V.sub.ref, a low level is output as the output signal V.sub.so of the differential amplifier 522. On the contrary, when the input signal V.sub.in is lower than the referential voltage V.sub.ref, a high level is output as the output signal V.sub.so of the differential amplifier 522. The output signal V.sub.so of the differential amplifier 522 is supplied to the inverter 521, the output V.sub.out of which is transmitted to the internal circuits of the MPU or memories.
When data is transmitted between the MPU 501 arid one of the memories 502, only the driver 503 or the receiver 504 of the one of the memories is activated, and the other drivers 503 and receivers 504 are not activated in the other memories 502. At that time, each of the drivers 503 and receivers 504 which are not activated is kept at a high impedance state. Also, in the one of the memories 502, while the driver 503 is activated, the receiver 504 is kept inactive to have a high impedance state. On the contrary, while the receiver 504 is activated, the driver 503 is kept inactive to have a high impedance state.
In operation of the conventional signal receiver as described above, when all the transistors in all of the drivers connected to the input/output line 508 are off, that is, when the input/output line 508 is not clamped to V.sub.cc or ground potential GND, a problem is involved therein from the viewpoint of electric power consumption. The problem is such that, when all of the transistors in the drivers 503 connected to the input/output line 508 are turned off, unnecessary transient oscillation is induced with the center of amplitude being around the referential voltage V.sub.ref.
FIG. 2A, 2B and 2C show the situation as described above, FIG. 2A showing the waveform of the input signal V.sub.in, FIG. 2B showing the output V.sub.so of the differential circuit and FIG. 2C showing the output V.sub.out of the inverter. At this time, the transient oscillation on the input/output line is amplified in the output V.sub.so of the differential amplifier, so that the output V.sub.so also has an unnecessary transient oscillation as shown in FIG. 2B. Further, the output V.sub.out from the inverter has a corresponding transient oscillation as shown in FIG. 2C.
The potential of the transient oscillation on the input/output line 508 resides around the referential voltage V.sub.ref. It may be considered that, in order to avoid signal transition of the output signal caused by the transient oscillation, even if the transient oscillation described above is induced, the differential amplifier should not respond to the oscillation so that the output V.sub.out from the inverter should be kept at a high or a low potential. However, in the conventional signal receiver, the above described problem cannot be avoided since the differential amplifier is designed to amplify, with a high sensitivity, a very small potential difference between the potential of the input signal V.sub.in and the referential voltage V.sub.ref.
The unnecessary transient oscillation causes unnecessary electric power consumption in the inverter and the other inverters or the like connected thereto. Thus, it is a serious problem in a semiconductor device which is required a low electric power consumption. For example, the current power consumption may reach a few mili-amperes (mA) even in a memory product such as a dynamic RAM designed to suppress a standby current below at a level of several tens of micro-amperes (.mu.A).